The advent of 3D Integrated Circuit technology has seen the convergence of particular processing methodologies for fabrication of 3D wafers. For example, a favored method of processing 3D through silicon via (TSV) wafers is to perform wafer thinning and processing of the TSV wafer while mounted to a glass wafer. This glass wafer provides a flat and stable platform which allows wafers to be thinned and processed and handled by existing wafer finishing and processing tools. The thinning and processing of the wafer is necessary to expose the through silicon vias which are only fabricated in approximately the first 60 μm of silicon on the active side of the wafer. Once exposed by a grinding operation (thinning implied), traditional wafer fabrication processes are used to connect to, isolate and passivate the connections and wiring.
For example, a glass carrier wafer onto which the TSV wafer to be thinned is attached with adhesive. The glass allows for the eventual separation of the carrier wafer and the thinned TSV wafer using a laser ablation process. In this process, a laser passes through the transparent glass and the energy is absorbed by the adhesive layer resulting in the ablation (vaporization) of the adhesive at the carrier/adhesive interface thereby releasing the bond of the adhesive. It is desirable to leave the thinned silicon wafer attached to the glass carrier wafer for the remainder of the processing including wafer level testing.
During wafer level testing, the bonded thin wafer and glass carrier wafer act as one mechanical unit and are placed on a wafer chuck and are probed with wafer scale test probes for testing purposes. However, there is a thermal problem associated with the glass carrier wafer which is now interposed between the wafer chuck and the device under test (the TSV wafer or chip site). Specifically, the glass carrier wafer has a thermal conductivity of 1.2 W/mK while a normal full thickness silicon wafer has a conductivity of 149 W/mK. This translates to a thermal resistance which is 100× worse with the glass. For any testing that requires high power (e.g., processors, dense logic, etc.), the temperature rise of the silicon under test becomes prohibitive. The glass carrier wafer is essentially a thermal insulator and, as a result, the temperature of a 3D wafer cannot be controlled during test, thereby preventing proper performance testing and also putting the device under test at risk. The risk is of self destruction of the device under test and/or of the probe assembly.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.